A semiconductor memory device may include a parity generating circuit, a memory cell array, an error calculating circuit and an error corrector. The parity generating circuit generates parities having different number of bits according to types of a partial array self-refresh mode, and selects one of the parities to output a first parity. The error calculating circuit calculates an error based on a first data corresponding to the input data and a second parity corresponding to the first parity and outputs a first error data. The error corrector corrects the first data based on the first data and the first error data.