Invention Grant
US08225258B2 Statistical integrated circuit package modeling for analysis at the early design age
有权
统计集成电路封装建模，用于在设计初期进行分析
- Patent Title: Statistical integrated circuit package modeling for analysis at the early design age
- Patent Title (中): 统计集成电路封装建模，用于在设计初期进行分析
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Application No.: US12482825Application Date: 2009-06-11
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Publication No.: US08225258B2Publication Date: 2012-07-17
- Inventor: Xiaoming Chen , Jack Monjay Yao
- Applicant: Xiaoming Chen , Jack Monjay Yao
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Michelle Gallardo; Nicholas J. Pauley; Jonathan T. Velasco
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
In designing an integrated circuit on a die having a set of die bumps, a method to generate a set of lumped circuit parameter values associated with the set of die bumps, based upon distances between the set of die bumps and the center of the die, the method also based upon a sample-data distribution function of a die bump distance variable and a sample-data distribution function of a lumped circuit parameter variable. Other embodiments are described and claimed.
Public/Granted literature
- US20100318955A1 Statistical Integrated Circuit Package Modeling For Analysis At The Early Design Age Public/Granted day:2010-12-16
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