Invention Grant
US08227304B2 Semiconductor-on-insulator (SOI) structure and method of forming the SOI structure using a bulk semiconductor starting wafer
有权
绝缘体上半导体(SOI)结构和使用体半导体起始晶片形成SOI结构的方法
- Patent Title: Semiconductor-on-insulator (SOI) structure and method of forming the SOI structure using a bulk semiconductor starting wafer
- Patent Title (中): 绝缘体上半导体(SOI)结构和使用体半导体起始晶片形成SOI结构的方法
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Application No.: US12710380Application Date: 2010-02-23
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Publication No.: US08227304B2Publication Date: 2012-07-24
- Inventor: Subramanian S. Iyer , Edward J. Nowak
- Applicant: Subramanian S. Iyer , Edward J. Nowak
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb & Riley, LLC
- Agent Richard M. Kotulak, Esq.
- Main IPC: H01L21/84
- IPC: H01L21/84 ; H01L21/20 ; H01L27/12

Abstract:
Disclosed is a method of forming a semiconductor-on-insulator (SOI) structure on a bulk semiconductor starting wafer. Parallel semiconductor bodies are formed at the top surface of the wafer. An insulator layer is deposited and recessed. Exposed upper portions of the semiconductor bodies are used as seed material for growing epitaxial layers of semiconductor material laterally over the insulator layer, thereby creating a semiconductor layer. This semiconductor layer can be used to form one or more SOI devices (e.g., a single-fin or multi-fin MUGFET or multiple series-connected single-fin or multi-fin MUGFETs). However, placement of SOI device components in and/or on portions of the semiconductor layer should be predetermined to avoid locations which might impact device performance (e.g., placement of any FET gate on a semiconductor fin formed from the semiconductor layer can be predetermined to avoid interfaces between joined epitaxial semiconductor material sections). Also disclosed is a SOI structure formed using the above-described method.
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