Invention Grant
- Patent Title: Semiconductor device
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Application No.: US12107599Application Date: 2008-04-22
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Publication No.: US08227900B2Publication Date: 2012-07-24
- Inventor: Kazuo Tomita
- Applicant: Kazuo Tomita
- Applicant Address: JP Kawasaki-shi
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2004-182366 20040621
- Main IPC: H01L23/544
- IPC: H01L23/544

Abstract:
The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.
Public/Granted literature
- US08330253B2 Semiconductor device Public/Granted day:2012-12-11
Information query
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