Invention Grant
- Patent Title: Flexible interconnect pattern on semiconductor package
- Patent Title (中): 半导体封装上的柔性互连图案
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Application No.: US13004815Application Date: 2011-01-11
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Publication No.: US08227907B2Publication Date: 2012-07-24
- Inventor: Yoshihiro Tomita , David Chau , Gregory M. Chrysler , Devendra Natekar
- Applicant: Yoshihiro Tomita , David Chau , Gregory M. Chrysler , Devendra Natekar
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L23/48 ; H01L29/40
Abstract:
An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.
Public/Granted literature
- US20110103438A1 FLEXIBLE INTERCONNECT PATTERN ON SEMICONDUCTOR PACKAGE Public/Granted day:2011-05-05
Information query
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