Invention Grant
US08227911B1 Method and structure of wafer level encapsulation of integrated circuits with cavity
有权
具有腔体的集成电路的晶片级封装的方法和结构
- Patent Title: Method and structure of wafer level encapsulation of integrated circuits with cavity
- Patent Title (中): 具有腔体的集成电路的晶片级封装的方法和结构
-
Application No.: US12634663Application Date: 2009-12-09
-
Publication No.: US08227911B1Publication Date: 2012-07-24
- Inventor: Xiao (Charles) Yang
- Applicant: Xiao (Charles) Yang
- Applicant Address: US CA San Jose
- Assignee: MCube Inc.
- Current Assignee: MCube Inc.
- Current Assignee Address: US CA San Jose
- Agency: Kilpatrick Townsend and Stockton LLP
- Main IPC: H01L23/10
- IPC: H01L23/10

Abstract:
The present invention is related shielding integrated devices using CMOS fabrication techniques to form an encapsulation with cavity. The integrated circuits are completed first using standard IC processes. A wafer-level hermetic encapsulation is applied to form a cavity above the sensitive portion of the circuits using IC-foundry compatible processes. The encapsulation and cavity provide a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment.
Information query
IPC分类: