Invention Grant
US08227911B1 Method and structure of wafer level encapsulation of integrated circuits with cavity 有权
具有腔体的集成电路的晶片级封装的方法和结构

Method and structure of wafer level encapsulation of integrated circuits with cavity
Abstract:
The present invention is related shielding integrated devices using CMOS fabrication techniques to form an encapsulation with cavity. The integrated circuits are completed first using standard IC processes. A wafer-level hermetic encapsulation is applied to form a cavity above the sensitive portion of the circuits using IC-foundry compatible processes. The encapsulation and cavity provide a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment.
Information query
Patent Agency Ranking
0/0