Invention Grant
- Patent Title: Routing layer for mitigating stress in a semiconductor die
- Patent Title (中): 用于减轻半导体管芯中的应力的路由层
-
Application No.: US12604584Application Date: 2009-10-23
-
Publication No.: US08227926B2Publication Date: 2012-07-24
- Inventor: Roden Topacio , Gabriel Wong
- Applicant: Roden Topacio , Gabriel Wong
- Applicant Address: CA Markham, Ontario
- Assignee: ATI Technologies ULC
- Current Assignee: ATI Technologies ULC
- Current Assignee Address: CA Markham, Ontario
- Agency: Faegre Baker Daniels LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.
Public/Granted literature
- US20110095415A1 ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE Public/Granted day:2011-04-28
Information query
IPC分类:
