A method for balancing clock signals in an IC layout includes obtaining a data-flow information of the IC, selecting a first data-flow according to the dataflow information, and synchronizing a first clock signal from a first register and a second clock signal from a second register involved in the first data-flow. The data processed by the first register is directly transmitted to the second register or transmitted through a combinational logic circuit to the second register. The first data-flow is not related to other data-flows included in the data-flow information.