Invention Grant
- Patent Title: Negative capacitance synthesis for use with differential circuits
- Patent Title (中): 用于差分电路的负电容合成
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Application No.: US12604955Application Date: 2009-10-23
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Publication No.: US08228120B2Publication Date: 2012-07-24
- Inventor: Peter J. Mole , Philip V. Golden
- Applicant: Peter J. Mole , Philip V. Golden
- Applicant Address: US CA Milpitas
- Assignee: Intersil Americas Inc.
- Current Assignee: Intersil Americas Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Fliesler Meyer LLP
- Main IPC: H03F3/45
- IPC: H03F3/45
Abstract:
Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.
Public/Granted literature
- US20100301940A1 NEGATIVE CAPACITANCE SYNTHESIS FOR USE WITH DIFFERENTIAL CIRCUITS Public/Granted day:2010-12-02
Information query
