Invention Grant
- Patent Title: Memory utilizing oxide nanolaminates
- Patent Title (中): 记忆利用氧化物Nanolaminates
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Application No.: US12790625Application Date: 2010-05-28
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Publication No.: US08228725B2Publication Date: 2012-07-24
- Inventor: Leonard Forbes , Kie Y. Ahn
- Applicant: Leonard Forbes , Kie Y. Ahn
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G11C16/00
- IPC: G11C16/00 ; G11C16/02 ; G11C16/04 ; H01L29/792

Abstract:
Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers.
Public/Granted literature
- US20100244122A1 MEMORY UTILIZING OXIDE NANOLAMINATES Public/Granted day:2010-09-30
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