Invention Grant
- Patent Title: Three-dimensionally stacked nonvolatile semiconductor memory
- Patent Title (中): 三维堆叠的非易失性半导体存储器
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Application No.: US13164938Application Date: 2011-06-21
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Publication No.: US08228733B2Publication Date: 2012-07-24
- Inventor: Naoya Tokiwa , Hideo Mukai
- Applicant: Naoya Tokiwa , Hideo Mukai
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2008-271279 20081021
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.
Public/Granted literature
- US20110249498A1 THREE-DIMENSIONALLY STACKED NONVOLATILE SEMICONDUTOR MEMORY Public/Granted day:2011-10-13
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