A memory circuit includes a first memory array, a second memory array and a switch module, wherein the first memory array has a first node and a second node, the second memory array has a third node and a fourth node, the first node is coupled to a first supply voltage, and the fourth supply voltage is coupled to a second supply voltage smaller than the first supply voltage. The switch module is coupled to the second node, the third node, the first supply voltage and the second supply voltage. When the memory circuit is operated under an inactive mode, the switch module electrically connects the second node to the third node, electrically disconnects the second node from the second supply voltage, and electrically disconnects the third node from the first supply voltage.