Invention Grant
US08230117B2 Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline
有权
在使用命令管道的一致性管理处理器系统中对写后排序进行排序的技术
- Patent Title: Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline
- Patent Title (中): 在使用命令管道的一致性管理处理器系统中对写后排序进行排序的技术
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Application No.: US12420889Application Date: 2009-04-09
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Publication No.: US08230117B2Publication Date: 2012-07-24
- Inventor: George William Daly, Jr. , Guy Lynn Guthrie , Ross Boyd Leavens , Joseph Gerald McDonald , Michael Steven Siegel , William John Starke , Derek Edward Williams
- Applicant: George William Daly, Jr. , Guy Lynn Guthrie , Ross Boyd Leavens , Joseph Gerald McDonald , Michael Steven Siegel , William John Starke , Derek Edward Williams
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Yudell Isidore Ng Russell PLLC
- Main IPC: G06F3/00
- IPC: G06F3/00
Abstract:
A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator is assigned to each of the I/O commands. The command location indicator provides an indication of which one of the I/O commands is a start command in the I/O stream and which of the I/O commands are continue commands in the I/O stream. The I/O commands are issued in a desired completion order. When a first one of the I/O commands does not complete successfully, the I/O commands in the I/O stream are reissued on the bus starting at the first one of the I/O commands that did not complete successfully.
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