A network processor is connected to an external memory which includes storage areas for storing received data, and stores descriptors specifying locations of the storage areas, respectively. The network processor includes a descriptor storage circuit for storing a plurality of descriptors out of the descriptors; a DMA control circuit configured to transfer the plurality of descriptors from the external memory to the descriptor storage circuit through DMA transfer, transfer the received data to the storage areas in the external memory through DMA transfer on a basis of the plurality of descriptors stored in the descriptor storage circuit upon receipt of the received data, and generate a reception status indicating a condition of the received data each time the received data is transferred to the external memory through DMA transfer, a reception status storage circuit for storing the reception status; and a reception status combination control circuit for combining the reception statuses which are stored in the reception status storage circuit. The DMA control circuit transfers the combined reception statuses to the external memory through DMA transfer.