Invention Grant
- Patent Title: Use of parity bits to detect memory installation defects
- Patent Title (中): 使用奇偶校验位来检测内存安装缺陷
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Application No.: US11138005Application Date: 2005-05-26
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Publication No.: US08230275B2Publication Date: 2012-07-24
- Inventor: Mark Shaw
- Applicant: Mark Shaw
- Applicant Address: US TX Houston
- Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee: Hewlett-Packard Development Company, L.P.
- Current Assignee Address: US TX Houston
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G01R31/28 ; G06F11/00 ; H03M13/00

Abstract:
Various systems and methods for detecting subsystem installation defects are provided. In one example method, a test value is generated in a detection tool to be applied to a subsystem through a plurality of interconnects. A first parity bit is then generated for the test value using the detection tool, and the test value is transmitted to the subsystem. A second parity bit is generated for the test value in the subsystem. Then, the first parity bit is compared with the second parity bit to determine if a fault exists in one of the interconnects.
Public/Granted literature
- US20060270259A1 Use of parity bits to detect memory installation defects Public/Granted day:2006-11-30
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