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US08230275B2 Use of parity bits to detect memory installation defects 有权
使用奇偶校验位来检测内存安装缺陷

Use of parity bits to detect memory installation defects
Abstract:
Various systems and methods for detecting subsystem installation defects are provided. In one example method, a test value is generated in a detection tool to be applied to a subsystem through a plurality of interconnects. A first parity bit is then generated for the test value using the detection tool, and the test value is transmitted to the subsystem. A second parity bit is generated for the test value in the subsystem. Then, the first parity bit is compared with the second parity bit to determine if a fault exists in one of the interconnects.
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