A Code Address Memory (CAM) cell read control circuit of a semiconductor memory device includes a CAM cell read circuit configured to read data stored in a CAM cell and to output the read data, an internal delay circuit configured to delay an externally input reset signal and to generate a number of internal command signals, and a signal generation unit configured to generate an internal ready/busy signal in response to the internal command signals. The internal ready/busy signal is generated after the externally input reset signal has reset the CAM cell read circuit.