Invention Grant
- Patent Title: Processor system using synchronous dynamic memory
- Patent Title (中): 处理器系统采用同步动态存储器
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Application No.: US13008189Application Date: 2011-01-18
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Publication No.: US08234441B2Publication Date: 2012-07-31
- Inventor: Kunio Uchiyama , Osamu Nishii
- Applicant: Kunio Uchiyama , Osamu Nishii
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP04-249190 19920918
- Main IPC: G06F12/00
- IPC: G06F12/00

Abstract:
A processor system including: a processor having a processor core and a controller core; and a plurality of synchronous memory chips, wherein the processor and the plurality of synchronous memory chips are connected via an external bus; wherein the processor core and the controller core are connected via an internal bus; wherein the plurality of synchronous memory chips are operated according to a clock signal; wherein the controller core comprises a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.
Public/Granted literature
- US20110314213A1 PROCESSOR SYSTEM USING SYNCHRONOUS DYNAMIC MEMORY Public/Granted day:2011-12-22
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