Invention Grant
- Patent Title: Serial interface device built-in self test
- Patent Title (中): 串行接口设备内置自检
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Application No.: US13110235Application Date: 2011-05-18
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Publication No.: US08234530B2Publication Date: 2012-07-31
- Inventor: Wayne Tseng
- Applicant: Wayne Tseng
- Applicant Address: TW Taipei Hsien
- Assignee: Via Technologies Inc.
- Current Assignee: Via Technologies Inc.
- Current Assignee Address: TW Taipei Hsien
- Agency: Thomas, Kayden, Horstemeyer & Risley, LLP
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F7/02 ; G01R31/28 ; G01R31/30 ; H03M13/00

Abstract:
A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.
Public/Granted literature
- US20110225470A1 Serial Interface Device Built-In Self Test Public/Granted day:2011-09-15
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