Invention Grant
- Patent Title: Circuit specification description visualizing device, circuit specification description visualizing method and storage medium
- Patent Title (中): 电路规格说明可视化装置,电路规格说明可视化方法和存储介质
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Application No.: US12578659Application Date: 2009-10-14
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Publication No.: US08234608B2Publication Date: 2012-07-31
- Inventor: Takashi Ishikawa
- Applicant: Takashi Ishikawa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Turocy & Watson, LLP
- Priority: JP2009-042877 20090225
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455

Abstract:
A design analyzing device includes a circuit specification description analyzing section configured to create structure data about an assertion description, a pass pattern creating section configured to create data about a plurality of pass patterns for which the assertion description passes from the structure data, a matching waveform calculating section configured to create waveform data for each signal in a circuit defined by the assertion description and correlation data that indicates a correlation between the waveform of each signal and a partial expression in the assertion description based on data of each of the plurality of pass patterns, and a display data outputting section configured to output display data about a diagram showing the correlation between each partial expression and the waveform of each signal for each pass pattern.
Public/Granted literature
Information query