Invention Grant
US08236653B2 Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions
有权
用于形成具有低电阻硅化物栅极和台面接触区域的MOSFET器件的配置和方法
- Patent Title: Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions
- Patent Title (中): 用于形成具有低电阻硅化物栅极和台面接触区域的MOSFET器件的配置和方法
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Application No.: US13361950Application Date: 2012-01-31
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Publication No.: US08236653B2Publication Date: 2012-08-07
- Inventor: Yongzhong Hu , Sung-Shan Tai
- Applicant: Yongzhong Hu , Sung-Shan Tai
- Applicant Address: BM
- Assignee: Alpha & Omega Semiconductor, LTD
- Current Assignee: Alpha & Omega Semiconductor, LTD
- Current Assignee Address: BM
- Agent Bo-In Lin
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A novel integration scheme for forming power MOSFET, particularly forming salicided layers for both gate contact regions and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicided layers.
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