A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.