Invention Grant
- Patent Title: High voltage high package pressure semiconductor package
- Patent Title (中): 高压高封装压力半导体封装
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Application No.: US12658576Application Date: 2010-02-09
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Publication No.: US08237171B2Publication Date: 2012-08-07
- Inventor: Tracy Autry
- Applicant: Tracy Autry
- Applicant Address: US CA Aliso Viejo
- Assignee: Microsemi Corporation
- Current Assignee: Microsemi Corporation
- Current Assignee Address: US CA Aliso Viejo
- Agency: Marger Johnson & McCollom PC
- Main IPC: H01L29/15
- IPC: H01L29/15

Abstract:
A hermetically sealed integrated circuit package that includes a cavity housing a semiconductor die, whereby the cavity is pressurized during assembly and when formed. The invention prevents the stress on a package created when the package is subject to high temperatures at atmospheric pressure and then cooled from reducing the performance of the die at high voltages. By packaging a die at a high pressure, such as up to 50 PSIG, in an atmosphere with an inert gas, and providing a large pressure in the completed package, the dies are significantly less likely to arc at higher voltages, allowing the realization of single die packages operable up to at least 1200 volts. Moreover, the present invention is configured to employ brazed elements compatible with Silicon Carbide dies which can be processed at higher temperatures.
Public/Granted literature
- US20110193098A1 High voltage high package pressure semiconductor package Public/Granted day:2011-08-11
Information query
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