An embodiment of the invention provides a package structure for chip. The package structure for chip includes: a carrier substrate having an upper surface and an opposite lower surface; a chip overlying the carrier substrate and having a first surface and an opposite second surface facing the upper surface, wherein the chip includes a first electrode and a second electrode; a first conducting structure overlying the carrier substrate and electrically connecting the first electrode; a second conducting structure overlying the carrier substrate and electrically connecting the second electrode; a first through-hole penetrating the upper surface and the lower surface of the carrier substrate and disposed next to the chip without overlapping the chip; a first conducting layer overlying a sidewall of the first through-hole and electrically connecting the first conducting electrode; and a third conducting structure overlying the carrier substrate and electrically connecting the second conducting structure.