Invention Grant
- Patent Title: Dummy gate structure for gate last process
- Patent Title (中): 门最后工序的虚拟门结构
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Application No.: US12455509Application Date: 2009-06-03
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Publication No.: US08237227B2Publication Date: 2012-08-07
- Inventor: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
- Applicant: Su-Chen Lai , Ming-Yuan Wu , Kong-Beng Thei , Harry Hak-Lay Chuang , Chiung-Han Yeh , Hong-Dyi Chang , Kuo Cheng Cheng , Chien-Hung Wu , Tzung-Chi Lee
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/70
- IPC: H01L21/70
Abstract:
A semiconductor device is provided which includes a semiconductor substrate having a first portion and a second portion, transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate, a device element formed in the second portion of the substrate, the device element being isolated by an isolation region, and a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.
Public/Granted literature
- US20100052060A1 Dummy gate structure for gate last process Public/Granted day:2010-03-04
Information query
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