Invention Grant
- Patent Title: Semiconductor device provided with tin diffusion inhibiting layer, and manufacturing method of the same
- Patent Title (中): 具有锡扩散抑制层的半导体装置及其制造方法
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Application No.: US13069771Application Date: 2011-03-23
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Publication No.: US08237277B2Publication Date: 2012-08-07
- Inventor: Hiroyasu Jobetto
- Applicant: Hiroyasu Jobetto
- Applicant Address: JP Tokyo
- Assignee: Casio Computer Co., Ltd.
- Current Assignee: Casio Computer Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz, Goodman & Chick, PC
- Priority: JP2010-066190 20100323; JP2010-070524 20100325
- Main IPC: H01L23/485
- IPC: H01L23/485
Abstract:
A semiconductor device is disclosed wherein a tin diffusion inhibiting layer is provided above the land of a wiring line, and a solder ball is provided above the tin diffusion inhibiting layer. Thus, even when this semiconductor device is, for example, a power supply IC which deals with a high current, the presence of the tin diffusion inhibiting layer makes it possible to more inhibit the diffusion of tin in the solder ball into the wiring line.
Public/Granted literature
- US20110233769A1 SEMICONDUCTOR DEVICE PROVIDED WITH TIN DIFFUSION INHIBITING LAYER, AND MANUFACTURING METHOD OF THE SAME Public/Granted day:2011-09-29
Information query
IPC分类:
