Invention Grant
US08237450B2 Method of testing insulation property of wafer-level chip scale package and TEG pattern used in the method
失效
该方法中使用的晶圆级芯片尺寸封装和TEG图案的绝缘性能测试方法
- Patent Title: Method of testing insulation property of wafer-level chip scale package and TEG pattern used in the method
- Patent Title (中): 该方法中使用的晶圆级芯片尺寸封装和TEG图案的绝缘性能测试方法
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Application No.: US12511375Application Date: 2009-07-29
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Publication No.: US08237450B2Publication Date: 2012-08-07
- Inventor: Kenji Nagasaki
- Applicant: Kenji Nagasaki
- Applicant Address: JP Tokyo
- Assignee: OKI Semiconductor Co., Ltd.
- Current Assignee: OKI Semiconductor Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Kubotera & Associates, LLC
- Priority: JP2008-213326 20080821
- Main IPC: G01R31/00
- IPC: G01R31/00 ; H01H31/12
Abstract:
A test element group (TEG) pattern formed of two wiring patterns alternately disposed in a swirl configuration is used for testing an insulation property of a wafer-level chip scale package (WL-CSP) having a micro wiring such as an inductor element. The insulation property of the WL-CSP can be monitored with enhanced accuracy by measuring a resistance value between solder terminals electrically connected to the swirl-shaped TEG pattern.
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