Invention Grant
- Patent Title: Method for wafer-level testing of integrated circuits
- Patent Title (中): 集成电路晶圆级测试方法
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Application No.: US12539328Application Date: 2009-08-11
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Publication No.: US08237462B2Publication Date: 2012-08-07
- Inventor: Tsung-Yang Hung , Aaron Wang
- Applicant: Tsung-Yang Hung , Aaron Wang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: G01R31/02
- IPC: G01R31/02 ; G01R31/26

Abstract:
A method for wafer level testing is provided which includes providing a wafer having an integrated circuit formed thereon, applying a signal to energize the integrated circuit, the signal including increasing steps or decreasing steps that range between a first level and a second level, and determining whether the integrated circuit complies with a test criteria after applying the signal.
Public/Granted literature
- US20110037494A1 Method for Wafer-Level Testing of Integrated Circuits Public/Granted day:2011-02-17
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