Invention Grant
US08237462B2 Method for wafer-level testing of integrated circuits 有权
集成电路晶圆级测试方法

Method for wafer-level testing of integrated circuits
Abstract:
A method for wafer level testing is provided which includes providing a wafer having an integrated circuit formed thereon, applying a signal to energize the integrated circuit, the signal including increasing steps or decreasing steps that range between a first level and a second level, and determining whether the integrated circuit complies with a test criteria after applying the signal.
Public/Granted literature
Information query
Patent Agency Ranking
0/0