An integrated circuit for controlling data output impedance includes an address decoder, a selection signal decoder, and a transfer control unit. The address decoder is configured to decode an address signal and generate a selection mode signal and a first adjustment mode signal. The selection signal decoder is configured to decode a selection signal and generate an enable signal and a disable signal. The transfer control unit is configured to transfer a pull-up signal and a pull-down signal as a selection pull-up signal and a selection pull-down signal.