Invention Grant
US08237473B2 Semiconductor integrated circuit device having plural delay paths and controller capable of blocking signal transmission in delay path 失效
具有多个延迟路径的半导体集成电路装置和能够阻止延迟路径中的信号传输的控制器

  • Patent Title: Semiconductor integrated circuit device having plural delay paths and controller capable of blocking signal transmission in delay path
  • Patent Title (中): 具有多个延迟路径的半导体集成电路装置和能够阻止延迟路径中的信号传输的控制器
  • Application No.: US12588993
    Application Date: 2009-11-04
  • Publication No.: US08237473B2
    Publication Date: 2012-08-07
  • Inventor: Masahiro Nomura
  • Applicant: Masahiro Nomura
  • Applicant Address: JP Kawasaki-shi, Kanagawa
  • Assignee: Renesas Electronics Corporation
  • Current Assignee: Renesas Electronics Corporation
  • Current Assignee Address: JP Kawasaki-shi, Kanagawa
  • Agency: McGinn IP Law Group, PLLC
  • Priority: JP2008-288846 20081111
  • Main IPC: H03L7/00
  • IPC: H03L7/00
Semiconductor integrated circuit device having plural delay paths and controller capable of blocking signal transmission in delay path
Abstract:
A plurality of delay paths are connected in parallel between two synchronous operation circuits operating in synchronism with a clock signal CLK, and enable transmission of a signal. A delay detection unit detects the respective delay times of the plurality of delay paths, and a control unit selects one delay path from among the plurality of delay paths based on the detection results from the delay detection unit, and controls the blocking of signal transmission in the delay paths other than the selected one delay path.
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