Invention Grant
US08237481B2 Low power programmable clock delay generator with integrated decode function
失效
具有集成解码功能的低功耗可编程时钟延迟发生器
- Patent Title: Low power programmable clock delay generator with integrated decode function
- Patent Title (中): 具有集成解码功能的低功耗可编程时钟延迟发生器
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Application No.: US12109728Application Date: 2008-04-25
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Publication No.: US08237481B2Publication Date: 2012-08-07
- Inventor: Yuen H. Chan , Rolf Sautter , Michael J. Lee , Juergen Pille
- Applicant: Yuen H. Chan , Rolf Sautter , Michael J. Lee , Juergen Pille
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent William A. Kinnaman, Jr.
- Main IPC: H03H11/26
- IPC: H03H11/26 ; G06F1/04 ; H03K17/284
Abstract:
A programmable Local Clock Buffer has a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch.
Public/Granted literature
- US20090267667A1 Low Power Programmable Clock Delay Generator with Integrated Decode Function Public/Granted day:2009-10-29
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