Invention Grant
US08237503B2 Output stage for a digital RF transmitter, method for providing an RF output signal in a digital RF transmitter, and digital RF transmitter 有权
用于数字RF发射器的输出级,用于在数字RF发射器中提供RF输出信号的方法以及数字RF发射器

  • Patent Title: Output stage for a digital RF transmitter, method for providing an RF output signal in a digital RF transmitter, and digital RF transmitter
  • Patent Title (中): 用于数字RF发射器的输出级,用于在数字RF发射器中提供RF输出信号的方法以及数字RF发射器
  • Application No.: US12921572
    Application Date: 2009-03-09
  • Publication No.: US08237503B2
    Publication Date: 2012-08-07
  • Inventor: Xin HeManel Collados AsensioNenad PavlovicJan Van Sinderen
  • Applicant: Xin HeManel Collados AsensioNenad PavlovicJan Van Sinderen
  • Applicant Address: NL Eindhoven
  • Assignee: NXP B.V.
  • Current Assignee: NXP B.V.
  • Current Assignee Address: NL Eindhoven
  • Priority: EP08102451 20080310
  • International Application: PCT/IB2009/050960 WO 20090309
  • International Announcement: WO2009/113000 WO 20090917
  • Main IPC: H03F3/26
  • IPC: H03F3/26
Output stage for a digital RF transmitter, method for providing an RF output signal in a digital RF transmitter, and digital RF transmitter
Abstract:
An output stage (1) for a digital RF transmitter is provided. The output stage comprises: an input adapted to receive an input signal (RFin, b7-b0) to be transmitted; a plurality N of power amplification sections (S1, S2, S3, S4); and an output (A, B) providing an output voltage signal. Each of the N power amplification sections (S1, S2, S3, S4) is arranged to receive the input signal (RFin, b7-b0) and comprises a transformer (T1, T2, T3, T4) adapted to provide a respective output signal. Each transformer comprises a primary stage and a secondary stage; the secondary stages of the transformers (T1, T2, T3, T4) of the N power amplification sections (S1, S2, S3, S4) are combined such that a combined output voltage signal of the output stage is provided. The N power amplification sections (S1, S2, S3, S4) are adapted such that the input signal (RFin, b7-b0) is latched by clock signals (clock1, clock2, clock3, clock4) comprising different phases.
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