Invention Grant
US08238154B2 Nonvolatile semiconductor memory with charge storage layers and control gates
有权
具有电荷存储层和控制栅极的非易失性半导体存储器
- Patent Title: Nonvolatile semiconductor memory with charge storage layers and control gates
- Patent Title (中): 具有电荷存储层和控制栅极的非易失性半导体存储器
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Application No.: US12552563Application Date: 2009-09-02
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Publication No.: US08238154B2Publication Date: 2012-08-07
- Inventor: Mario Sako , Jun Fujimoto , Noriyasu Kumazaki , Yasuhiko Honda , Yoshihiko Kamata
- Applicant: Mario Sako , Jun Fujimoto , Noriyasu Kumazaki , Yasuhiko Honda , Yoshihiko Kamata
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2009-044003 20090226
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage.
Public/Granted literature
- US20100214837A1 NONVOLATILE SEMICONDUCTOR MEMORY WITH CHARGE STORAGE LAYERS AND CONTROL GATES Public/Granted day:2010-08-26
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