Invention Grant
US08238191B2 Dual port PLD embedded memory block to support read-before-write in one clock cycle
失效
双端口PLD嵌入式内存块,支持在一个时钟周期内进行预写入
- Patent Title: Dual port PLD embedded memory block to support read-before-write in one clock cycle
- Patent Title (中): 双端口PLD嵌入式内存块,支持在一个时钟周期内进行预写入
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Application No.: US12687823Application Date: 2010-01-14
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Publication No.: US08238191B2Publication Date: 2012-08-07
- Inventor: Haiming Yu
- Applicant: Haiming Yu
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Womble Carlyle Sandridge & Rice, LLP
- Main IPC: G11C8/00
- IPC: G11C8/00

Abstract:
A method for a read-before-write functionality for a memory within a programmable logic device (PLD) is provided. The method begins when a read operation and a write operation are initiated through two different ports of a memory simultaneously to access the same address in the memory. In order to prevent the write operation from proceeding prior to the read operation, a read-before-write control logic is provided to the control block of the port that supports the write operation. Thus, the write operation is paused until the control block of the port that supports the write operation receives a signal from a read sense amplifier indicating that the read operation is complete. The read sense amplifier is capable of detecting the completion of a read operation by monitoring the voltage difference of the read bitline. When this voltage difference reaches a threshold value, the read sense amplifier triggers a write wordline signal. The enabling of the write wordline signal causes, the data to be written to the memory.
Public/Granted literature
- US20100157691A1 Dual Port PLD Embedded Memory Block to Support Read-Before-Write in One Clock Cycle Public/Granted day:2010-06-24
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