Invention Grant
US08238414B1 Sliding error sampler (SES) for latency reduction in the PWM path 有权
滑动误差采样器(SES)用于PWM路径中的延迟降低

  • Patent Title: Sliding error sampler (SES) for latency reduction in the PWM path
  • Patent Title (中): 滑动误差采样器(SES)用于PWM路径中的延迟降低
  • Application No.: US11904025
    Application Date: 2007-09-25
  • Publication No.: US08238414B1
    Publication Date: 2012-08-07
  • Inventor: Hee Wong
  • Applicant: Hee Wong
  • Applicant Address: US CA Santa Clara
  • Assignee: National Semiconductor Corporation
  • Current Assignee: National Semiconductor Corporation
  • Current Assignee Address: US CA Santa Clara
  • Agent Eugene C. Conser; Wade J. Brady, III; Frederick J. Telecky, Jr.
  • Main IPC: H03K7/08
  • IPC: H03K7/08
Sliding error sampler (SES) for latency reduction in the PWM path
Abstract:
A digital control loop within power switchers and the like includes a sliding error sampler pulse width modulation timing variably setting a number of clock cycles relative to a digital pulse width modulator output trailing edge for loading control variables for a filter. A computation time for the proportional-integral-derivative filter is predicted based on an average for previous digital pulse width modulator outputs, computed within the integral path for the previous loop iteration. A margin is added to accommodate transient conditions accelerating the trailing edge of the digital pulse width modulator output, either fixed or variable depending on the previous iteration pulse width.
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