Invention Grant
- Patent Title: Semiconductor integrated circuit
- Patent Title (中): 半导体集成电路
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Application No.: US12783320Application Date: 2010-05-19
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Publication No.: US08238440B2Publication Date: 2012-08-07
- Inventor: Hiroshige Abe , Isamu Mochizuki , Mika Mizutani
- Applicant: Hiroshige Abe , Isamu Mochizuki , Mika Mizutani
- Applicant Address: JP Kawasaki-shi
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi
- Agency: Miles & Stockbridge P.C.
- Priority: JP2009-130939 20090529
- Main IPC: H04N11/04
- IPC: H04N11/04

Abstract:
The present invention is directed to lessen burden at the time of solving a conflict of overlapping processes in processes for a plurality of interruption factors. On completion of data transfer to an external memory, a data transfer completion interruption of high priority is generated. In the case where data transfer of predetermined number of packets is not completed in reception interruption, a timer interruption of low priority is generated. Before processing data in an external memory responding to the interruption, the number of transfer packets is obtained from a counter. After restart of reception, the counter stores the number of transfer restart packets. After obtaining the number of transfer packets from a counter responding to the occurrence of the timer interruption, a data transfer completion interruption is generated. According to the obtained number of transfer packets, execution of either a process responding to occurrence of the timer interruption or a process responding to occurrence of the data transfer completion interruption is omitted.
Public/Granted literature
- US20100303157A1 SEMICONDUCTOR INTEGRATED CIRCUIT Public/Granted day:2010-12-02
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