Invention Grant
- Patent Title: Circuit for synchronizing serial communication channels
- Patent Title (中): 串行通信通道同步电路
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Application No.: US12367011Application Date: 2009-02-06
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Publication No.: US08238452B1Publication Date: 2012-08-07
- Inventor: Mrinal J. Sarmah
- Applicant: Mrinal J. Sarmah
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agent LeRoy D. Maunu
- Main IPC: H04L27/00
- IPC: H04L27/00

Abstract:
Circuits are provided for synchronizing serial communication channels having respective receivers, of which one is a master receiver. Each receiver includes a FIFO buffer and a synchronizing element. The FIFO buffer is written periodically with characters received from the serial communication channel of the receiver, and the FIFO buffer is read periodically, except between the start and end of synchronization of the receiver. The start of synchronization of the master receiver is generated from the timing of reading a channel bonding character from the FIFO buffer of the master receiver. The start of synchronization of each receiver other than the master receiver is generated after the start of the master receiver and in response to reading a channel bonding character from the FIFO buffer of the receiver. The end of synchronization of the receivers is generated a time interval after the start of the master receiver.
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