The invention relates to a method or to a correspondingly equipped circuit for line-coupled generation of a clock (t), wherein the clock (t) is controlled in relation to a synchronization signal (hs) and by means of a closed loop (FLL) with respect to the phase and/or the frequency in relation to the synchronization signal (hs); wherein a plurality (n) of at least two count values (cn, c0-c7) is determined, wherein each of the count values (cn, c0-c7) is determined with at least one count duration number (z) of consecutive periods of the synchronization signal (hs), and wherein each of the count values (cn, c0-c7) is determined offset relative to at least one further count value (cn, c0-c7) with a count offset (v) which is different from the count duration number of consecutive periods of the synchronization signal (hs).