Invention Grant
- Patent Title: Hierarchical memory architecture to connect mass storage devices
- Patent Title (中): 连接大容量存储设备的分层内存架构
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Application No.: US12415991Application Date: 2009-03-31
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Publication No.: US08239629B2Publication Date: 2012-08-07
- Inventor: Sean Eilert
- Applicant: Sean Eilert
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G06F12/00
- IPC: G06F12/00
Abstract:
A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count.
Public/Granted literature
- US20100250849A1 HIERARCHICAL MEMORY ARCHITECTURE TO CONNECT MASS STORAGE DEVICES Public/Granted day:2010-09-30
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