Invention Grant
US08239658B2 Internally derived address generation system and method for burst loading of a synchronous memory
有权
用于突发加载同步存储器的内部派生地址生成系统和方法
- Patent Title: Internally derived address generation system and method for burst loading of a synchronous memory
- Patent Title (中): 用于突发加载同步存储器的内部派生地址生成系统和方法
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Application No.: US11359205Application Date: 2006-02-21
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Publication No.: US08239658B2Publication Date: 2012-08-07
- Inventor: Stefan-Cristian Rezeanu
- Applicant: Stefan-Cristian Rezeanu
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G06F9/26
- IPC: G06F9/26 ; G06F9/34 ; G06F13/00 ; G06F13/28 ; G06F12/00

Abstract:
An address generation system and method is provided for internally storing and thereafter producing an address to be sent to a memory device. The address that is stored need not be sent from an external address bus at each clock cycle, but the processing can remain internal to the memory device. The burst-block starting address can be stored in the mirror register and output from a selector circuit, such as a multiplexer, when that address is chosen. Otherwise, the multiplexer can simply perform its normal operation of selecting between an address pointed to by a counter, the external address, or the incremented counter output, based on the state of the external counter control signals. The system includes a mirror register, a counter, and a multiplexer that selects either the mirror register stored address or the internally processed address.
Public/Granted literature
- US20070198807A1 Internally derived address generation system and method for burst loading of a synchronous memory Public/Granted day:2007-08-23
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