A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.