Invention Grant
US08241952B2 Semiconductor device and method of forming IPD in fan-out level chip scale package
有权
半导体器件和在扇出级芯片级封装中形成IPD的方法
- Patent Title: Semiconductor device and method of forming IPD in fan-out level chip scale package
- Patent Title (中): 半导体器件和在扇出级芯片级封装中形成IPD的方法
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Application No.: US12713018Application Date: 2010-02-25
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Publication No.: US08241952B2Publication Date: 2012-08-14
- Inventor: Yaojian Lin , Robert C. Frye , Pandi Chelvam Marimuthu , Kai Liu
- Applicant: Yaojian Lin , Robert C. Frye , Pandi Chelvam Marimuthu , Kai Liu
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins & Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48 ; H01L21/50

Abstract:
A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive layer. A first insulating layer is formed over the die and resistive layer. The wafer is singulated to separate the die. The die is mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. The carrier and a portion of the encapsulant and first insulating layer is removed. A second insulating layer is formed over the encapsulant and first insulating layer. A second conductive layer is formed over the first and second insulating layers. A third insulating layer is formed over the second insulating layer and second conductive layer. A third conductive layer is formed over the third insulating layer and second conductive layer. A fourth insulating layer is formed over the third insulating layer and third conductive layer.
Public/Granted literature
- US20110204509A1 Semiconductor Device and Method of Forming IPD in Fan-Out Level Chip Scale Package Public/Granted day:2011-08-25
Information query
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