Invention Grant
US08245102B1 Error checking parity and syndrome of a block of data with relocated parity bits
有权
错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验
- Patent Title: Error checking parity and syndrome of a block of data with relocated parity bits
- Patent Title (中): 错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验
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Application No.: US12188939Application Date: 2008-08-08
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Publication No.: US08245102B1Publication Date: 2012-08-14
- Inventor: Warren E. Cory , David P. Schultz , Steven P. Young
- Applicant: Warren E. Cory , David P. Schultz , Steven P. Young
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agent W. Eric Webostad; Gerald Chan
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.
Information query