Invention Grant
US08254071B2 Method and apparatus of providing 2-stage ESD protection for high-speed interfaces
有权
为高速接口提供2级ESD保护的方法和设备
- Patent Title: Method and apparatus of providing 2-stage ESD protection for high-speed interfaces
- Patent Title (中): 为高速接口提供2级ESD保护的方法和设备
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Application No.: US12180440Application Date: 2008-07-25
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Publication No.: US08254071B2Publication Date: 2012-08-28
- Inventor: Jeff Dunnihoo , Richard Kimoto
- Applicant: Jeff Dunnihoo , Richard Kimoto
- Applicant Address: US AZ Phoenix
- Assignee: Semiconductor Components Industries, LLC
- Current Assignee: Semiconductor Components Industries, LLC
- Current Assignee Address: US AZ Phoenix
- Agency: Pillsbury Winthrop Shaw Pittman LLP
- Main IPC: H02H9/00
- IPC: H02H9/00 ; H02H7/12 ; H02H1/00 ; H02H1/04 ; H02H3/22 ; H02H9/06

Abstract:
The present invention relates to a method and apparatus of providing 2-stage ESD protection for high-speed interfaces. An aspect of the present invention is to provide an integrated multi-stage ESD/EOS protection solution for such high-speed applications. In one embodiment, the ESD protection device has multiple ESD stages integrated into a single integrated circuit package and is mounted to a printed circuit board in series with a device under protection. In another embodiment the multiple ESD stages integrated into a single integrated circuit package of the ESD protection device are coupled with a series element that isolates a 2nd stage from a 1st stage during an ESD event, thus ensuring that the 2nd stage turns on before the 1st stage, as well as provides for less current in the 2nd stage.
Public/Granted literature
- US20090046401A1 METHOD AND APPARATUS OF PROVIDING 2-STAGE ESD PROTECTION FOR HIGH-SPEED INTERFACES Public/Granted day:2009-02-19
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