Invention Grant
- Patent Title: Integrated circuit including doped semiconductor line having conductive cladding
- Patent Title (中): 集成电路包括具有导电包层的掺杂半导体线
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Application No.: US12206439Application Date: 2008-09-08
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Publication No.: US08254166B2Publication Date: 2012-08-28
- Inventor: Ulrich Klosterman , Ulrike Gruening-von Schwerin , Franz Kreupl
- Applicant: Ulrich Klosterman , Ulrike Gruening-von Schwerin , Franz Kreupl
- Applicant Address: DE Munich
- Assignee: Qimonda AG
- Current Assignee: Qimonda AG
- Current Assignee Address: DE Munich
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: G11C11/36
- IPC: G11C11/36 ; H01L21/441
Abstract:
An integrated circuit includes an array of memory cells. Each memory cell includes a diode. The integrated circuit includes a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of diodes. The integrated circuit includes conductive cladding contacting the doped semiconductor line.
Public/Granted literature
- US20100061140A1 INTEGRATED CIRCUIT INCLUDING DOPED SEMICONDUCTOR LINE HAVING CONDUCTIVE CLADDING Public/Granted day:2010-03-11
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