Invention Grant
US08255752B2 Clock domain check method, clock domain check program, and recording medium
失效
时钟域检查方式,时钟域检查程序和记录介质
- Patent Title: Clock domain check method, clock domain check program, and recording medium
- Patent Title (中): 时钟域检查方式,时钟域检查程序和记录介质
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Application No.: US12505924Application Date: 2009-07-20
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Publication No.: US08255752B2Publication Date: 2012-08-28
- Inventor: Keiichi Suzuki , Susumu Abe
- Applicant: Keiichi Suzuki , Susumu Abe
- Applicant Address: JP Kawasaki-shi
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi
- Agency: Miles & Stockbridge P.C.
- Priority: JP2008-211458 20080820
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G06F11/00

Abstract:
To reduce pseudo errors, a stationary signal is propagated through the circuit to be checked. A combination is extracted in which different asynchronous transfers occur between a transmitting side register and a receiving side register. From the extracted combination of asynchronous transfers, a circuit to be checked is extracted, and a synchronization circuit of a plurality of signals is excluded from the circuit to be checked. A stationary signal is propagated through the circuit to be checked, for each combination among all combinations of logic values “1” and “0” of the stationary signal. It is checked whether or not there exists one asynchronous transmitting side register to which signal change can logically reach, in the combination of logic values of the stationary signal propagated. Based on the result, it is determined whether or not the circuit is appropriate as a synchronization circuit for a single-signal transfer, thereby reducing pseudo errors.
Public/Granted literature
- US20100050061A1 CLOCK DOMAIN CHECK METHOD, CLOCK DOMAIN CHECK PROGRAM, AND RECORDING MEDIUM Public/Granted day:2010-02-25
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