Invention Grant
- Patent Title: Method and system for verification of multi-voltage circuit design
- Patent Title (中): 多电压电路设计验证方法及系统
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Application No.: US12467955Application Date: 2009-05-18
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Publication No.: US08255859B2Publication Date: 2012-08-28
- Inventor: Harsh Chilwal , Srikanth Jadcherla , Sriram Kotni , Prapanna Tiwari
- Applicant: Harsh Chilwal , Srikanth Jadcherla , Sriram Kotni , Prapanna Tiwari
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Park, Vaughan, Fleming & Dowler LLP
- Agent Laxman Sahasrabuddhe
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455
Abstract:
Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
Public/Granted literature
- US20090228852A1 METHOD AND SYSTEM FOR VERIFICATION OF MULTI-VOLTAGE CIRCUIT DESIGN Public/Granted day:2009-09-10
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