Invention Grant
- Patent Title: Substrate joining method and 3-D semiconductor device
- Patent Title (中): 基板接合方法和3-D半导体器件
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Application No.: US12540764Application Date: 2009-08-13
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Publication No.: US08257528B2Publication Date: 2012-09-04
- Inventor: Fujio Yagihashi , Yoshitaka Hamada , Takeshi Asano
- Applicant: Fujio Yagihashi , Yoshitaka Hamada , Takeshi Asano
- Applicant Address: JP Tokyo
- Assignee: Shin-Etsu Chemical Co., Ltd.
- Current Assignee: Shin-Etsu Chemical Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2008-209194 20080815
- Main IPC: B32B37/00
- IPC: B32B37/00 ; B32B9/04 ; C09J163/00 ; C09J5/06 ; C09J201/00 ; H01L21/20 ; H01L21/50 ; H01L21/52
Abstract:
A pair of substrates each having a bonding surface are joined together by interposing a bond layer precursor coating between the bonding surfaces of the substrates and heating the precursor coating to form a bond layer. Prior to the joining step, the substrate on the bonding surface is provided with a gas-permeable layer. Even when a material which will evolve a noticeable volume of gas upon heat curing is used as the precursor coating, substrates can be joined via a robust bond without the peeling problem by gas evolution.
Public/Granted literature
- US20100040893A1 SUBSTRATE JOINING METHOD AND 3-D SEMICONDUCTOR DEVICE Public/Granted day:2010-02-18
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