Invention Grant
- Patent Title: Method for fabricating stacked semiconductor components
- Patent Title (中): 层叠半导体元件的制造方法
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Application No.: US12265032Application Date: 2008-11-05
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Publication No.: US08258006B2Publication Date: 2012-09-04
- Inventor: Alan G. Wood
- Applicant: Alan G. Wood
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agent Stephen A. Gratton
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48 ; H01L21/50 ; H01L21/4763

Abstract:
A semiconductor component includes a carrier and multiple semiconductor substrates stacked and interconnected on the carrier. The carrier includes conductive members bonded to corresponding conductive openings on the semiconductor substrates. The component can also include terminal contacts on the carrier in electrical communication with the conductive members, and an outer member for protecting the semiconductor substrates. A method for fabricating the component includes the steps of providing the carrier with the conductive members, and providing the semiconductor substrates with the conductive openings. The method also includes the step of aligning and placing the conductive openings on the conductive members, and then bonding the conductive members to the conductive openings. A system includes the carrier having the conductive members, the semiconductor substrates having the conductive openings, an aligning and placing system for aligning and placing the semiconductor substrates on the carrier, and a bonding system for bonding the conductive members to the conductive openings.
Public/Granted literature
- US20090068791A1 Method For Fabricating Stacked Semiconductor Components Public/Granted day:2009-03-12
Information query
IPC分类: