Invention Grant
- Patent Title: Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications
- Patent Title (中): 具有特别适用于模拟应用的场效应晶体管的半导体架构的制造
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Application No.: US13298284Application Date: 2011-11-16
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Publication No.: US08258026B2Publication Date: 2012-09-04
- Inventor: Constantin Bulucea
- Applicant: Constantin Bulucea
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
An insulated-gate field-effect transistor (220U) is provided with an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.
Public/Granted literature
Information query
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