Invention Grant
- Patent Title: Charge-trap based memory
- Patent Title (中): 基于充电陷阱的存储器
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Application No.: US12548193Application Date: 2009-08-26
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Publication No.: US08258034B2Publication Date: 2012-09-04
- Inventor: Nirmal Ramaswamy , Gurtej S. Sandhu
- Applicant: Nirmal Ramaswamy , Gurtej S. Sandhu
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/792
Abstract:
Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described.
Public/Granted literature
- US20110049606A1 CHARGE-TRAP BASED MEMORY Public/Granted day:2011-03-03
Information query
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